module RAM (
    input wire clka,
    input wire ena,
    input wire wea,
    input wire [14:0] addra,
    input wire [31:0] dina,
    output reg [31:0] douta,
    input wire clkb,
    input wire enb,
    input wire web,
    input wire [14:0] addrb,
    input wire [31:0] dinb,
    output reg [31:0] doutb
);
    
endmodule